1. Field of the Invention
The present invention relates to the field of high voltage PMOS circuits. Specifically, the present invention relates to level shifter circuits having complimentary low voltage inputs and complementary high voltage outputs.
2. Discussion of the Related Art
Due to device limitations, conventional level shifter circuits for high voltage operations are prone to breaking down when high voltage is present. Specifically, MOSFET parameters which may limit conventional circuits ability to handle high voltage are the oxide breakdown voltage, the punch-through breakdown voltage, and the junction breakdown voltage.
The oxide breakdown voltage is the gate to source or the gate to drain voltage at which the gate oxide ruptures. For example, the gate oxide breakdown voltage of a modern device with gate oxide thicknesses of about 150 Angstroms is approximately 12 volts. However, with sufficient gate oxide thicknesses, destructive gate oxide ruptures are eliminated.
The punch-through breakdown voltage is the drain to source or source to drain voltage at which the drain current abruptly increases. Continued operation in this condition may generate enough heat to damage the MOSFET. The punch-through breakdown can be prevented by constructing the gate length of the MOSFET longer then the drain to source or source to drain depletion length.
Even when the parameters of a MOSFET are adequate to overcome oxide and punch-through breakdowns, a junction breakdown can still occur. The junction breakdown voltage is the drain or source to substrate voltage that is the level of reverse bias between the drain or source and the substrate at which the reverse-biased diode junction used for electrical isolation of the drain or source breaks down due to avalanching or Zener behavior. For a typical modern device parameters, the junction breakdown voltage for a standard transistor having a 10 volt gate to substrate voltage is about 10 volts. At this gate voltage level, as the gate voltage rises, the junction breakdown voltage increases approximately linearly with the gate voltage by a factor of about 1.0 times the gate to substrate voltage.
As is apparent from the above discussion, a need exists for a high voltage PMOS level shifter which allows switching to occur during high voltage operation without violating any breakdown limitations, especially the junction breakdown limitation.